The present application relates generally to methods for forming semiconductor devices, and is particularly applicable to improving a density of features for the 14 nanometer technology node and beyond.
A trend in the development of semiconductor manufacturing technologies has been to increase the density of devices per chip, and hence decrease the size of active structures as well as the distances between such structures. An increase in device density may advantageously affect device performance such as circuit speed, and may allow also for increasingly complex designs and functionality. However, the decrease in size and the attendant increase in density pose various manufacturing challenges, including the precise alignment of middle-of-the-line (MOL) metallization structures. Large contact areas and loose enclosure rules between underlying and overlying layers of metallization facilitate ease of alignment and enable low resistance and high yield, but incur a scaling penalty.
In advanced node devices such as FinFET devices, for instance, tight enclosure rules such as between source/drain interconnects and overlying conductive contacts enable extended scaling, but are susceptible to process variability and high electrical resistance between the conductive structures, which can adversely affect yield. Notwithstanding recent developments, it would be beneficial to develop methods of forming conductive contacts that meet next-generation performance and scaling requirements.